HD6417750RF240DV Datasheet, PDF (544/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
• Burst Read
Figure 13.43 is the timing chart of a burst-read operation with a burst length of 4. Following
the Tr cycle, during which an ACTV command is output, a READ command is issued during
cycle Tc1, and a READA command is issued four cycles later. During the Td1 to Td8 cycles,
read data are accepted on the rising edges of the external command clock (CKIO). Tpc is the
cycle used to wait for the auto-precharging, which is triggered by the READA command, to be
completed in the synchronous DRAM. During this cycle, a new command for accessing the
same bank cannot be issued. In the SH7750R, the number of Tpc cycles is determined by the
setting of the TPC2 to TPC0 bits of MCR, and no command that operates on the synchronous
DRAM may be issued during these cycles.
CKIO
Tr
Trw
Tc1
Tc2
Tc3 Tc4/Td1 Td2
Td3
Td4
Td5
Td6
Td7
Td8
Tpc
Bank
Row
Precharge-sel
Row
H/L
H/L
Address
Row
c1
c5
CSn
RD/WR
RAS
CASS
DQMn
D31–D0 (read)
BS
CKE
DACKn
(SA: IO ← memory)
c1
c2
c3
c4
c5
c6
c7
c8
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4)
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013