HD6417750RF240DV Datasheet, PDF (907/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 20 User Break Controller (UBC)
20.2.2 Break Address Register A (BARA)
Bit: 31
BAA31
Initial value: *
R/W: R/W
30
BAA30
*
R/W
29
BAA29
*
R/W
28
BAA28
*
R/W
27
BAA27
*
R/W
26
BAA26
*
R/W
25
BAA25
*
R/W
24
BAA24
*
R/W
Bit: 23
BAA23
Initial value: *
R/W: R/W
22
BAA22
*
R/W
21
BAA21
*
R/W
20
BAA20
*
R/W
19
BAA19
*
R/W
18
BAA18
*
R/W
17
BAA17
*
R/W
16
BAA16
*
R/W
Bit: 15
BAA15
Initial value: *
R/W: R/W
14
BAA14
*
R/W
13
BAA13
*
R/W
12
BAA12
*
R/W
11
BAA11
*
R/W
10
BAA10
*
R/W
9
BAA9
*
R/W
8
BAA8
*
R/W
Bit: 7
BAA7
Initial value: *
R/W: R/W
Legend: *: Undefined
6
BAA6
*
R/W
5
BAA5
*
R/W
4
BAA4
*
R/W
3
BAA3
*
R/W
2
BAA2
*
R/W
1
BAA1
*
R/W
0
BAA0
*
R/W
Break address register A (BARA) is a 32-bit readable/writable register that specifies the virtual
address used in the channel A break conditions. BARA is not initialized by a power-on reset or
manual reset.
Bits 31 to 0—Break Address A31 to A0 (BAA31–BAA0): These bits hold the virtual address
(bits 31–0) used in the channel A break conditions.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 855 of 1076