HD6417750RF240DV Datasheet, PDF (490/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
13.3.3 SRAM Interface
Basic Timing: The SRAM interface of this LSI uses strobe signal output in consideration of the
fact that mainly SRAM will be connected. Figure 13.6 shows the basic timing of normal space
accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one
cycle to indicate the start of a bus cycle. The CSn signal is asserted on the T1 rising edge, and
negated on the next T2 clock rising edge. Therefore, there is no negation period in case of access
at minimum pitch.
There is no access size specification when reading. The correct access address is output to the
address pins (A[25:0]), but since there is no access size specification, 32 bits are always read in
the case of a 32-bit device, and 16 bits in the case of a 16-bit device. When writing, only the WE
signal for the byte to be written is asserted. For details, see section 13.3.1, Endian/Access Size and
Data Alignment.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wrap around mode on the data at the 32-byte boundary. The bus is not
released during this transfer.
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Sep 24, 2013