HD6417750RF240DV Datasheet, PDF (61/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
1.2 Block Diagram
Figure 1.1 shows an internal block diagram of this LSI.
Section 1 Overview
CPU
UBC
FPU
Lower 32-bit data
Lower 32-bit data
SH-4 Core
I cache
Cache and
ITLB
TLB
UTLB
controller
O cache
CPG
INTC
SCI
(SCIF)
RTC
TMU
BSC
DMAC
External
bus interface
26-bit
address
64-bit
data
Legend:
BSC: Bus state controller
CPG: Clock pulse generator
DMAC: Direct memory access controller
FPU: Floating-point unit
INTC: Interrupt controller
ITLB: Instruction TLB (translation lookaside buffer)
UTLB:
RTC:
SCI:
SCIF:
TMU:
UBC:
Unified TLB (translation lookaside buffer)
Realtime clock
Serial communication interface
Serial communication interface with FIFO
Timer unit
User break controller
Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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