HD6417750RF240DV Datasheet, PDF (596/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Conditions Under which Problem Occurs
a. The partial-sharing master mode is selected (BCR1.PSHR = 1).
b. Refresh is enabled for area 3 (BCR1.DRAMTP[2:0] = 010, 011, or 101; MCR.RFSH = 1;
MCR.RMODE = 0).
c. Except for refresh requests, no requests to access external memory (chip-internal requests
by the CPU or DMAC to access areas 0 to 6) have been issued to the bus status controller
following access to the shared area, area 2.
d. MCR.TRC is set to a value other than 0 (MCR.TRC[2:0] ≠ 000).
Example: If the refresh cycle is approximately 4,096 times/64 ms, one refresh takes place every 15
µs or so. Therefore, the master mode device’s bus performance may be decreased by 3 to 21 CKIO
cycles every 15 µs or so when the master mode device responds to a bus request.
In addition, if the master mode device is using the bus when BSREQ is asserted, BSACK may
not be asserted immediately. In this case the above problem has little effect on the master
mode device.
Workarounds: Methods 1. or 2. below can be used as workarounds if degradation of the bus
performance of the master mode device due to the phenomenon described above poses a problem.
1. Set MCR.TRC[2:0] to 0 0 0.
2. Store the program in an area other than area 2, and insert an instruction to perform a
dummy access to external memory (area 0, 1, or 3 to 6) immediately after the instruction
accessing area 2.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013