HD6417750RF240DV Datasheet, PDF (657/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
14.5.2 Pins in DDT Mode
Figure 14.24 shows the system configuration in DDT mode.
SH7750, SH7750S, SH7750R
DBREQ/DREQ0
BAVL/DRAK0
TR/DREQ1
TDACK/DACK0
ID1, ID0/DRAK1, DACK1
CKIO
D63–D0=DTR
External device
A25–A0, RAS, CAS, WE, DQMn, CKE
Synchronous
DRAM
Figure 14.24 System Configuration in On-Demand Data Transfer Mode
• DBREQ: Data bus release request signal for transmitting the data transfer request format (DTR
format) or a DMA request from an external device to the DMAC
If there is a wait for release of the data bus, an external device can have the data bus released
by asserting DBREQ. When DBREQ is accepted, the BSC asserts BAVL.
• BAVL: Data bus D63–D0 release signal
Assertion of BAVL means that the data bus will be released two cycles later.
This LSI does not switch the data pins to output status for a total of three cycles: the cycle in
which the data bus is released and the cycles preceding and following it.
• TR: Transfer request signal
Assertion of TR has the following different meanings.
⎯ In normal data transfer mode (channel 0, except channel 0), TR is asserted, and at the same
time the DTR format is output, two cycles after BAVL is asserted.
⎯ In the case of the handshake protocol without use of the data bus, asserting TR enables a
transfer request to be issued for the channel for which a transfer request was made
immediately before. This function can be used only when BAVL is not asserted two cycles
earlier.
⎯ In the case of direct data transfer mode (valid only for channel 2), a direct transfer request
can be made to channel 2 by asserting DBREQ and TR simultaneously.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 605 of 1076