HD6417750RF240DV Datasheet, PDF (611/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or
active-low.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is
invalid.
Bit 16: AL
0
1
Description
Active-high output
Active-low output
(Initial value)
Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify
incrementing/decrementing of the DMA transfer destination address. The specification of these
bits is ignored when data is transferred from external memory to an external device in single
address mode. For channel 0, in DDT mode these bits are set to DM1 = 0 and DM0 = 1 with the
DTR format.
Bit 15: DM1
0
1
Bit 14: DM0
0
1
0
1
Description
Destination address fixed
(Initial value)
Destination address incremented (+1 in 8-bit transfer, +2 in 16-
bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in
32-byte burst transfer)
Destination address decremented (–1 in 8-bit transfer, –2 in
16-bit transfer, –4 in 32-bit transfer, –8 in 64-bit transfer, –32 in
32-byte burst transfer)
Setting prohibited
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 559 of 1076