HD6417750RF240DV Datasheet, PDF (912/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 20 User Break Controller (UBC)
SH7750, SH7750S, SH7750R Group
Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31–
0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or
manual reset.
Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be
used in the channel B break conditions.
20.2.10 Break Data Mask Register B (BDMRB)
Bit: 31
30
29
28
27
26
25
24
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24
Initial value: *
*
*
*
*
*
*
*
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
19
18
17
16
BDMB2 BDMB2 BDMB2 BDMB2 BDMB1 BDMB1 BDMB1 BDMB1
3
2
1
0
9
8
7
6
Initial value: *
*
*
*
*
*
*
*
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
BDMB1 BDMB1 BDMB1 BDMB1 BDMB1 BDMB1 BDMB9 BDMB8
5
4
3
2
1
0
Initial value: *
*
*
*
*
*
*
*
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0
Initial value: *
*
*
*
*
*
*
*
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Legend: *: Undefined
Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which
bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on
reset or manual reset.
Page 860 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013