HD6417750RF240DV Datasheet, PDF (616/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 14 Direct Memory Access Controller (DMAC)
SH7750, SH7750S, SH7750R Group
14.2.5 DMA Operation Register (DMAOR)
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
DDT
—
—
—
—
—
PR1 PR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R/W R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
COD
—
AE NMIF DME
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/(W)
R
R/(W) R/(W) R/W
Notes: The AE and NMIF bits can only be written with 0 after being read as 1, to clear the flags.
The COD bit can be written to in the SH7750S only.
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0.
Page 564 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013