HD6417750RF240DV Datasheet, PDF (554/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed on the data at the 32-byte boundary. The bus is not released during this
period.
Table 13.18 Relationship between Address and CE when Using PCMCIA Interface
Bus
Width
(Bits)
8
16
Access
Read/ Size Odd/
Write (Bits)^*1 Even
Read 8
Even
Odd
16
Even
Even
Odd
Write 8
Even
Odd
16
Even
Even
Odd
Read 8
Even
Odd
16
Even
Odd
Write 8
Even
Odd
16
Even
Odd
IOIS16 Access CE2 CE1 A0
Don't —
100
care
Don't —
care
101
Don't First 1 0 0
care
Don't Second 1 0 1
care
Don't —
———
care
Don't —
100
care
Don't —
101
care
Don't First 1 0 0
care
Don't Second 1 0 1
care
Don't —
———
care
Don't —
100
care
Don't —
011
care
Don't —
000
care
Don't —
———
care
Don't —
100
care
Don't —
011
care
Don't —
care
000
Don't —
———
care
D15–D8
Invalid
D7–D0
Read data
Invalid
Read data
Invalid
Lower read data
Invalid
Upper read data
—
—
Invalid
Write data
Invalid
Write data
Invalid
Lower write data
Invalid
Upper write data
—
—
Invalid
Read data
Read data
Invalid
Upper read data Lower read data
—
—
Invalid
Write data
Write data
Invalid
Upper write data Lower write data
—
—
Page 502 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013