HD6417750RF240DV Datasheet, PDF (597/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
Section 14 Direct Memory Access Controller (DMAC)
14.1 Overview
The SH7750 and SH7750S include an on-chip four-channel direct memory access controller
(DMAC). The SH7750R includes an on-chip eight-channel DMAC. The DMAC can be used in
place of the CPU to perform high-speed data transfers among external devices equipped with
DACK (TMU, SCI, SCIF), external memories, memory-mapped external devices, and on-chip
peripheral modules (except the DMAC, BSC, and UBC). Using the DMAC reduces the burden on
the CPU and increases the operating efficiency of the chip. When using the SH7750R, see the
following sections:
Section 14.6, Configuration of DMAC (SH7750R);
Section 14.7, Register Descriptions (SH7750R);
Section 14.8, Operation (SH7750R).
14.1.1 Features
The DMAC has the following features.
• Four channels (SH7750/SH7750S), eight channels (SH7750R)
• Physical address space
• Choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length
• Maximum of 16 M (16,777,216) transfers
• Choice of single or dual address mode
⎯ Single address mode: Either the transfer source or the transfer destination (external device)
is accessed by a DACK signal while the other is accessed by address. One data transfer is
completed in one bus cycle.
⎯ Dual address mode: Both the transfer source and transfer destination are accessed by
address. Values set in DMAC internal registers indicate the accessed address for both the
transfer source and the transfer destination. Two bus cycles are required for one data
transfer.
• Choice of bus mode: Cycle steal mode or burst mode
• Two types of DMAC channel priority ranking:
⎯ Fixed priority mode: Channel priorities are permanently fixed.
⎯ Round robin mode: Sets the lowest priority for the channel for which an execution request
was last accepted.
• An interrupt request can be sent to the CPU on completion of the specified number of
transfers.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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