HD6417750RF240DV Datasheet, PDF (289/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 8 Pipelining
40. Double-precision FCMP: 2 issue cycles
FCMP/EQ,FCMP/GT
I
D
F1
F2
FS
D
F1
F2
FS
41. Double-precision FDIV/SQRT: 1 issue cycle
FDIV, FSQRT
I
D
F1
F2
FS
d
F1
F2
F3
42. FIPR: 1 issue cycle
F1
F2
FS
F1
F2
FS
F1
F2
FS
I
D
F0
F1
F2
FS
43. FTRV: 1 issue cycle
I
D
F0
F1
F2
FS
d
F0
F1
F2
FS
d
F0
F1
F2
FS
d
F0
F1
F2
FS
Notes:
?? ^{: Cannot overlap a stage of the same kind, except when two instructions are}
executed in parallel.
D : Locks D-stage
d : Register read only
?? : Locks, but no operation is executed.
f1 : Can overlap another f1, but not another F1.
Figure 8.2 Instruction Execution Patterns (cont)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 237 of 1076