HD6417750RF240DV Datasheet, PDF (864/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 18 I/O Ports
SH7750, SH7750S, SH7750R Group
Table 18.2 shows the SCI I/O port pin configuration.
Table 18.2 SCI I/O Port Pins
Pin Name
Abbreviation
I/O
Function
Serial clock pin
MD0/SCK
I/O
Clock input/output
Receive data pin
RxD
Input
Receive data input
Transmit data pin
MD7/TxD
Output
Transmit data output
Note:
Pins MD0/SCK and MD7/TxD function as mode input pins MD0 and MD7 after a power-on
reset. They are made to function as serial pins by performing SCI operation settings with
the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/A bit in SCSMR1. Break state
transmission and detection can be performed by means of a setting in the SCI's SCSPTR1
register.
Table 18.3 shows the SCIF I/O port pin configuration.
Table 18.3 SCIF I/O Port Pins
Pin Name
Abbreviation
I/O
Function
Serial clock pin
MRESET/SCK2 Input
Clock input
Receive data pin
MD2/RxD2
Input
Receive data input
Transmit data pin
Modem control pin
MD1/TxD2
CTS2
Output
I/O
Transmit data output
Transmission enabled
Modem control pin MD8/RTS2
I/O
Transmission request
Note:
The MRESET/SCK2 pin functions as the MRESET manual reset pin when a manual reset is
executed. The MD1/TxD2, MD2/RxD2, and MD8/RTS2 pins function as the MD1, MD2, and
MD8 mode input pins after a power-on reset. These pins are made to function as serial pins
by performing SCIF operation settings with the TE and RE bits in SCSCR2 and the MCE bit
in SCFCR2. Break state transmission and detection can be set in the SCIF's SCSPTR2
register.
Page 812 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013