HD6417750RF240DV Datasheet, PDF (453/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
13.2.8 Memory Control Register (MCR)
The memory control register (MCR) is a 32-bit readable/writable register that specifies RAS and
CAS timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address
multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected
without using external circuitry.
MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits RASD, MRSET, TRC2–0, TPC2–0, RCD1–0, TRWL2–0, TRAS2–0, BE,
SZ1–0, AMXEXT, AMX2–0, and EDOMODE are written in the initialization following a power-
on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the
same values should be written to the other bits so that they remain unchanged. When using DRAM
or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is
completed.
Bit: 31
30
29
28
27
26
25
24
RASD MRSET TRC2 TRC1 TRC0
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W
R
R
R
Bit: 23
22
21
20
19
18
17
16
TCAS
—
TPC2 TPC1 TPC0
—
RCD1 RCD0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R/W R/W R/W
R
R/W R/W
Bit: 15
14
13
12
11
10
9
8
TRWL2 TRWL1 TRWL0 TRAS2 TRAS1 TRAS0 BE
SZ1
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
SZ0 AMXEXT AMX2 AMX1 AMX0 RFSH RMODE EDO
MODE
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 401 of 1076