HD6417750RF240DV Datasheet, PDF (192/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 4 Caches
SH7750, SH7750S, SH7750R Group
The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to
the way and the entry set in the address field. The A bit in the address field should be cleared
to 0.
When a write is performed to a cache line for which the U bit and V bit are both 1, after write-
back of that cache line, the tag, U bit, and V bit specified in the data field are written.
3. OC address array write (associative)
When a write is performed with the A bit in the address field set to 1, the tag for each of the
ways stored in the entry specified in the address field is compared with the tag specified in the
data field. The way number set by bit [14] is not used. If the MMU is enabled at this time,
comparison is performed after the virtual address specified by data field bits [31:10] has been
translated to a physical address using the UTLB. If the addresses match and the V bit for that
way is 1, the U bit and V bit specified in the data field are written into the OC entry. This
operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If
the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If
an UTLB miss occurs during address translation, or the comparison shows a mismatch, an
exception is not generated, no operation is performed, and the write is not executed. If a data
TLB multiple hit exception occurs during address translation, processing switches to the data
TLB multiple hit exception handling routine.
31
24 23
Address field _{1 1 1 1 0 1 0 0}
31
Data field
Tag
15 14 13
Way
Entry
10 9
Legend:
V: Validity bit
U: Dirty bit
A: Association bit
: Reserved bits (0 write value, undefined read value)
Figure 4.14 Memory-Mapped OC Address Array
543210
A
210
UV
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013