HD6417750RF240DV Datasheet, PDF (889/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 19 Interrupt Controller (INTC)
19.3.2 Interrupt Control Register (ICR)
The interrupt control register (ICR) is a 16-bit register that sets the input signal detection mode for
external interrupt input pin NMI and indicates the input signal level at the NMI pin. This register
is initialized by a power-on reset or manual reset. It is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
Bit name: NMIL MAI
—
—
—
—
NMIB NMIE
Initial value: 0/1*
0
0
0
0
0
0
0
R/W: R
R/W
—
—
—
—
R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: IRLM
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
—
—
—
—
—
—
—
Note: * 1 when NMI pin input is high, 0 when low.
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. It cannot be modified.
Bit 15: NMIL
0
1
Description
NMI pin input level is low
NMI pin input level is high
Bit 14—NMI Interrupt Mask (MAI): Specifies whether or not all interrupts are to be masked
while the NMI pin input level is low, irrespective of the CPU's SR.BL bit.
Bit 14: MAI
Description
0
Interrupts enabled even while NMI pin is low
(Initial value)
1
Interrupts disabled while NMI pin is low*
Note: * NMI interrupts are accepted in normal operation and in sleep mode.
In standby mode, all interrupts are masked, and standby is not cleared, while the NMI
pin is low.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 837 of 1076