HD6417750RF240DV Datasheet, PDF (444/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Bits 31 to 29—Area 6 Wait Control (A6W2—A6W0): These bits specify the number of wait
states to be inserted for area 6. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Bit 31: A6W2
0
1
Bit 30: A6W1
0
1
0
1
Bit 29: A6W0
0
1
0
1
0
1
0
1
Description
First Cycle
Inserted Wait States
RDY Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
6
Enabled
9
Enabled
12
Enabled
15 (Initial value)
Enabled
Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to
be inserted from the second data access onward in a burst transfer with the burst ROM interface
selected.
Bit 28: A6B2
0
1
Bit 27: A6B1
0
1
0
1
Bit 26: A6B0
0
1
0
1
0
1
0
1
Description
Burst Cycle (Excluding First Cycle)
Wait States Inserted
from Second Data
Access Onward
RDY Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
4
Enabled
5
Enabled
6
Enabled
7 (Initial value)
Enabled
Page 392 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013