HD6417750RF240DV Datasheet, PDF (858/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 18 I/O Ports
SH7750, SH7750S, SH7750R Group
SCI I/O port block diagrams are shown in figures 18.3 to 18.5.
MD0/SCK
Mode setting
register
Reset
R
QD
SPB1IO
C
SPTRW
Reset
QR _D
SPB1DT
C
SPTRW
Internal data bus
SCI
Clock output enable signal
Serial clock output signal _*
Serial clock input signal
Clock input enable signal
SPTRR
Legend:
SPTRW: Write to SPTR
SPTRR: Read SPTR
Note: * Signals that set the SCK pin function as internal clock output or external clock input according to
the CKE0 and CKE1 bits in SCSCR1 and the C/A bit in SCSMR1.
Figure 18.3 MD0/SCK Pin
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013