HD6417750RF240DV Datasheet, PDF (400/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 12 Timer Unit (TMU)
SH7750, SH7750S, SH7750R Group
Bits 7 and 6—Input Capture Control (ICPE1, ICPE0) (Channel 2 Only): These bits, provided
in channel 2 only, specify whether the input capture function is used, and control enabling or
disabling of interrupt generation when the function is used.
When the input capture function is used, a data transfer request is sent to the DMAC in the event
of input capture.
When using the input capture function, the TCLK pin must be designated as an input pin with the
TCOE bit in the TOCR register. The CKEG bits specify whether the rising edge or falling edge of
the TCLK signal is used to set the TCNT2 value in the input capture register (TCPR2).
The TCNT2 value is set in TCPR2 only when the TCR2.ICPF bit is 0. When the TCR2.ICPF bit is
1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer
request is generated regardless of the value of the TCR2.ICPF bit. However, a new DMAC
transfer request is not generated until processing of the previous request is finished.
Bit 7: ICPE1
0
1
Bit 6: ICPE0
0
1
0
1
Description
Input capture function is not used
(Initial value)
Reserved (Do not set)
Input capture function is used, but interrupt due to input
capture (TICPI2) is not enabled
Data transfer request is sent to DMAC in the event of input
capture
Input capture function is used, and interrupt due to input
capture (TICPI2) is enabled
Data transfer request is sent to DMAC in the event of input
capture
Bit 5—Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt
generation when the UNF status flag is set to 1, indicating TCNT underflow.
Bit 5: UNIE
0
1
Description
Interrupt due to underflow (TUNI) is not enabled
Interrupt due to underflow (TUNI) is enabled
(Initial value)
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013