HD6417750RF240DV Datasheet, PDF (1112/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Appendix F Synchronous DRAM Address Multiplexing Tables
SH7750, SH7750S, SH7750R Group
(22) BUS 32 (16M: 256k × 32b × 2) × 1 *
AMX 7 16M, column-addr-8bit
2MB
LSI Address Pins
Synchronous DRAM
RAS Cycle CAS Cycle
Address Pins
Function
A13
A12
A20
A20
A10
BANK selects bank address
A11
A19
H/L
A9
Address precharge setting
A10
A18
0
A8
Address
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
Not used
A0
Not used
Note: * Example of a synchronous DRAM configuration
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013