HD6417750RF240DV Datasheet, PDF (155/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 3 Memory Management Unit (MMU)
3.7.1 ITLB Address Array
The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, V, and ASID to be written to the address array are
specified in the data field.
In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array, and the
entry is selected by bits [9:8]. As longword access is used, 0 should be specified for address field
bits [1:0].
In the data field, VPN is indicated by bits [31:10], V by bit [8], and ASID by bits [7:0].
The following two kinds of operation can be used on the ITLB address array:
1. ITLB address array read
VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry
set in the address field.
2. ITLB address array write
VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to
the entry set in the address field.
31
24 23
Address field _{1 1 1 1 0 0 1 0}
10 9 8 7
0
E
31
Data field
VPN
10 9 8 7
0
V
ASID
Legend:
VPN: Virtual page number
V: Validity bit
E: Entry
ASID: Address space identifier
: Reserved bits (0 write value, undefined
read value)
Figure 3.13 Memory-Mapped ITLB Address Array
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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