HD6417750RF240DV Datasheet, PDF (855/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 18 I/O Ports
Section 18 I/O Ports
18.1 Overview
This LSI has a 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port.
18.1.1 Features
The features of the general-purpose I/O port are as follows:
• 20-bit I/O port with input/output direction independently specifiable for each bit
• Pull-up can be specified independently for each bit.
• Interrupt input is possible for 16 of the 20 I/O port bits.
• Use or non-use of the I/O port can be selected with the PORTEN bit in bus control register 2
(BCR2).
The features of the SCI I/O port are as follows:
• Data can be output when the I/O port is designated for output and SCI enabling has not been
set. This allows break function transmission.
• The RxD pin value can be read at all times, allowing break state detection.
• SCK pin control is possible when the I/O port is designated for output and SCI enabling has
not been set.
• The SCK pin value can be read at all times.
The features of the SCIF I/O port are as follows:
• Data can be output when the I/O port is designated for output and SCIF enabling has not been
set. This allows break function transmission.
• The RxD2 pin value can be read at all times, allowing break state detection.
• CTS2 and RTS2 pin control is possible when the I/O port is designated for output and SCIF
enabling has not been set.
• The CTS2 and RTS2 pin values can be read at all times.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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