 English |
|
|
|
|
|
|
|
| HD6417750RF240DV Datasheet, PDF (585/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series | |||
| |||
| ◁ |
SH7750, SH7750S, SH7750R Group
T1
CKIO
Section 13 Bus State Controller (BSC)
Tw
Twe
T2
A25âA0
CSn
RD/WR
RD
D63âD0
(read)
WEn
BS
RDY
DACKn
(SA: IO â memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.77 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External
Wait)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 533 of 1076
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese