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| HD6417750RF240DV Datasheet, PDF (1025/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series | |||
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SH7750, SH7750S, SH7750R Group
Section 22 Electrical Characteristics
CKIO
BANK
Precharge-sel
Address
CSn
RD/WR
Tnop
(Tnop)
Tc1
Tc2
Tc3
Tc4
Trwl
Trwl
tAD
Row
H/L
c0
tCSD
tRWD
tRWD
tAD
tCSD
RAS
CASS
DQMn
D63âD0
(write)
BS
tCASD2
tCASD2
tWDD
tDQMD
tWDD
tWDD
d0
d1
tBSD
tBSD
tDQMD
d2
d3
CKE
DACKn
(SA: IO â memory)
tDACD
Legend:
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
SA-DMA
Normal write
tDACD
Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the
solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the
dotted line.
Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst
(RASD = 1, TRWL[2:0] = 010)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 973 of 1076
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