HD6417750RF240DV Datasheet, PDF (633/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer
conditions in this example are dual address mode and DREQ level detection.
DREQ
Bus returned to CPU
Bus cycle
CPU
CPU
CPU DMAC DMAC CPU DMAC DMAC CPU
Read Write
Read Write
CPU
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode
Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers
data continuously until the transfer end condition is satisfied. With DREQ low level detection in
external request mode, however, when DREQ is driven high the bus passes to another bus master
after the end of the DMAC transfer request that has already been accepted, even if the transfer end
condition has not been satisfied.
Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in
this example are single address mode and DREQ level detection (CHCRn.DS = 0, CHCRn.TM =
1).
DREQ
Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Figure 14.10 Example of DMA Transfer in Burst Mode
Note: Burst mode can be set regardless of the transfer size. A 32-byte block transfer burst mode
setting can also be made.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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