HD6417750RF240DV Datasheet, PDF (210/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 5 Exceptions
SH7750, SH7750S, SH7750R Group
5.5.3 Exception Requests and BL Bit
When the BL bit in SR is 0, general exception and interrupts are accepted.
When the BL bit in SR is 1 and a general exception other than a user break is generated, the CPU's
internal registers and the registers of the other modules are set to their states following a manual
reset, and the CPU branches to the same address as in a reset (H'A000 0000). For the operation in
the event of a user break, see section 20, User Break Controller (UBC).
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL
bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held
pending or accepted according to the setting made by software.
Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable
multiple exception state acceptance.
5.5.4 Return from Exception Handling
The RTE instruction is used to return from exception handling. When the RTE instruction is
executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns
from the exception handling routine by branching to the SPC address. If SPC and SSR were saved
to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and
issuing the RTE instruction.
5.6 Description of Exceptions
The various exception handling operations are described here, covering exception sources,
transition addresses, and processor operation when a transition is made.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013