HD6417750RF240DV Datasheet, PDF (431/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM
interface is used in area 6. When burst ROM interface is used, they also specify the number of
accesses in a burst. If area 6 is an MPX interface area, these bits are ignored.
Bit 7: A6BST2
0
Bit 6: A6BST1
0
Bit 5: A6BST0
0
1
1
0
1
1
0
0
1
1
0
1
Notes: Clear to 0 when PCMCIA interface is set.
* Settable only for SH7750R.
Description
Area 6 is accessed as SRAM interface
(Initial value)
Area 6 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, 32-, or 64*-bit
bus width
Area 6 is accessed as burst ROM
interface (8 consecutive accesses)
Can only be used with 8-, 16-, or 32-bit
bus width
Area 6 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
Area 6 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
Reserved
Reserved
Reserved
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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