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HD6417750RF240DV Datasheet, PDF (57/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series | |||
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SH7750, SH7750S, SH7750R Group
Section 1 Overview
Item
Features
Cache memory
⢠Instruction cache (IC)
[SH7750, SH7750S] ⯠8 Kbytes, direct mapping
⯠256 entries, 32-byte block length
⯠Normal mode (8-Kbyte cache)
⯠Index mode
⢠Operand cache (OC)
⯠16 Kbytes, direct mapping
⯠512 entries, 32-byte block length
⯠Normal mode (16-Kbyte cache)
⯠Index mode
⯠RAM mode (8-Kbyte cache + 8-Kbyte RAM)
⯠Choice of write method (copy-back or write-through)
⢠Single-stage copy-back buffer, single-stage write-through buffer
⢠Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
⢠Store queue (32 bytes à 2 entries)
Cache memory
[SH7750R]
⢠Instruction cache (IC)
⯠16 Kbytes, 2-way set associative
⯠256 entries/way, 32-byte block length
⯠Cache-double-mode (16-Kbyte cache)
⯠Index mode
⯠SH7750/SH7750S-compatible mode (8 Kbytes, direct mapping)
⢠Operand cache (OC)
⯠32 Kbytes, 2-way set associative
⯠512 entries/way, 32-byte block length
⯠Cache-double-mode (32-Kbyte cache)
⯠Index mode
⯠RAM mode (16-Kbyte cache + 16-Kbyte RAM)
⯠SH7750/SH7750S-compatible mode (16 Kbytes, direct mapping)
⢠Single-stage copy-back buffer, single-stage write-through buffer
⢠Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
⢠Store queue (32 bytes à 2 entries)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 5 of 1076
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