HD6417750RF240DV Datasheet, PDF (397/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 12 Timer Unit (TMU)
The TCNT registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual
reset, but are not initialized and retain their contents in standby mode. The TCNT registers for
channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not
initialized and retain their contents on a manual reset and in standby mode.
Bit: 31
30
29
2
1
0
·············
Initial value: 1
1
1
1
1
1
R/W: R/W R/W R/W
R/W R/W R/W
When the input clock is the on-chip RTC output clock (RTCCLK) in channels 0 to 2, TCNT
counts even in module standby mode (that is, when the clock for the TMU is stopped). When the
input clock is the external clock (TCLK) or internal clock (Pck), TCNT contents are retained in
standby mode.
12.2.6 Timer Control Registers (TCR)
The TCR registers are 16-bit readable/writable registers. There are five TCR registers, one for
each channel.
Each TCR selects the count clock, specifies the edge when an external clock is selected in
channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (TCNT)
underflow is set to 1. TCR2 is also used for channel 2 input capture control, and control of
interrupt generation in the event of input capture.
The TCR registers for channels 0 to 2 are initialized to H'0000 by a power-on or manual reset, but
are not initialized and retain their contents in standby mode. The TCR registers for channels 3 and
4 of the SH7750R are initialized to H'0000 by a power-on reset, but are not initialized and retain
their contents on a manual reset and in standby mode.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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