HD6417750RF240DV Datasheet, PDF (395/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 12 Timer Unit (TMU)
12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only)
TSTR2 is an 8-bit readable/writable register that specifies whether the channels 3−4 timer
counters (TSTR2) run or are stopped.
TSTR2 is initialized to H'00 by a power-on reset and retains its value in standby mode. If standby
mode is entered when the STR3 or STR4 bit is set to 1, counting is halted at the same time as the
peripheral module clock is stopped. Counting is restarted on resumption of the clock-signal
supply.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
STR4 STR3
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
Bits 7 to 2—Reserved: These bits are always read as 0. Writing to these bits is invalid. If a value
is written to these bits, it should always be 0.
Bit 1—Counter Start 4 (STR4): Specifies whether timer counter 4 (TCNT4) runs or is stopped.
Bit 1: STR4
0
1
Description
Counting by TCNT4 is stopped
Counting by TCNT4 proceeds
(Initial value)
Bit 0—Counter Start 3 (STR3): Specifies whether timer counter 3 (TCNT3) runs or is stopped.
Bit 0: STR3
0
1
Description
Counting by TCNT3 is stopped
Counting by TCNT3 proceeds
(Initial value)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 343 of 1076