HD6417750RF240DV Datasheet, PDF (188/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 4 Caches
SH7750, SH7750S, SH7750R Group
4.6 Memory-Mapped Cache Configuration (SH7750R)
To enable the management of the IC and OC by software, a program running in the privileged
mode is allowed to access their contents.
The contents of IC can be read and written by using MOV instructions in a P2-area program
running in the privileged mode. Operation is not guaranteed for access from a program in some
other area. Any branching to other areas must take place at least 8 instructions after this MOV
instruction.
The contents of IC can be read and written by using MOV instructions in a P1- or P2-area
program running in the privileged mode. Operation is not guaranteed if access is attempted from a
program running in some other area. A branch to the P0, U0, or P3 area must be made at least 8
instructions after this MOV instruction.
The IC and OC are allocated to the P4 area of the physical memory space. The address and data
arrays of both the IC and OC are only accessible by their data fields. Longword operations must
be used. Instruction fetches from these areas are not possible. For reserved bits, a write value of 0
should be specified; values read from such bits are undefined. Note that, in the SH7750/SH7750S-
compatible mode, the configuration of the SH7750R's memory-mapped cache is the same as that
of the SH7750 or SH7750S.
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Sep 24, 2013