HD6417750RF240DV Datasheet, PDF (898/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 19 Interrupt Controller (INTC)
SH7750, SH7750S, SH7750R Group
19.5 Interrupt Response Time
The time from generation of an interrupt request until interrupt exception handling is performed
and fetching of the first instruction of the exception service routine is started (the interrupt
response time) is shown in table 19.9.
Table 19.9 Interrupt Response Time
Number of States
Item
NMI
RL
Peripheral
Modules
Notes
Time for priority decision and 1Icyc + 4Bcyc 1Icyc + 7Bcyc 1Icyc + 2Bcyc
SR mask bit comparison*
Wait time until end of
sequence being executed by
CPU
S – 1 (≥ 0) ×
Icyc
S – 1 (≥ 0) ×
Icyc
S – 1 (≥ 0) ×
Icyc
Time from interrupt exception
handling (save of SR and
PC) until fetch of first
instruction of exception
handler is started
4 × Icyc
4 × Icyc
4 × Icyc
Response
time
Total
5Icyc + 4Bcyc 5Icyc + 7Bcyc 5Icyc + 2Bcyc
+ (S – 1)Icyc + (S – 1)Icyc + (S – 1)Icyc
Minimum
case
13Icyc
19Icyc
9Icyc
When Icyc:
Bcyc = 2:1
Maximum
case
36 + S Icyc
60 + S Icyc
20 + S Icyc
When Icyc:
Bcyc = 8:1
Legend:
Icyc: One cycle of internal clock supplied to CPU, etc.
Bcyc: One CKIO cycle
S: Latency of instruction
Note: * In the SH7750 and SH7750S including the case where the mask bit (IMASK) in SR is
changed, and a new interrupt is generated.
Page 846 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013