HD6417750RF240DV Datasheet, PDF (459/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
• For Synchronous DRAM Interface:
AMX
AMXEXT SZ
Example of Synchronous DRAM BANK^*4
0
0
64
(16M: 512K × 16 bits × 2) × 4
a[22]^*1
32
(16M: 512K × 16 bits × 2) × 2
a[21]^*1
1
64
(16M: 512K × 16 bits × 2) × 4
a[21]^*1
32
(16M: 512K × 16 bits × 2) × 2
a[20]^*1
1
0
64
(16M: 1M × 8 bits × 2) × 8
a[23]^*1
32
(16M: 1M × 8 bits × 2) × 4
a[22]^*1
1
64
(16M: 1M × 8 bits × 2) × 8
a[22]^*1
32
(16M: 1M × 8 bits × 2) × 4
a[21]^*1
2
—
64
(64M: 1M × 16 bits × 4) × 4
a[24:23]^*1
32
(64M: 1M × 16 bits × 4) × 2
a[23:22]^*1
3
—
64
(64M: 2M × 8 bits × 4) × 8
a[25:24]^*1
32
(64M: 2M × 8 bits × 4) × 4
a[24:23]^*1
4
—
64
(64M: 512K × 32 bits × 4) × 2
a[23:22]^*1
32
(64M: 512K × 32 bits × 4) × 1
a[22:21]^*1
5
—
64
(64M: 1M × 32 bits × 2) × 2
a[23]^*1
32
(64M: 1M × 32 bits × 2) × 1
a[22]^*1
6
0
64
(128M: 4M × 8 bits × 4) × 8^*2
a[26:25]^*1
1
64
(256M: 4M × 16 bits × 4) × 4^*2
a[26:25]^*1
0
32
(128M: 4M × 8 bits × 4) × 4^*3
a[25:24]^*1
1
32
(256M: 4M × 16 bits × 4) × 2^*3
a[25:24]^*1
7
—
64
(16M: 256K × 32 bits × 2) × 2
a[21]^*1
32
(16M: 256K × 32 bits × 2) × 1
a[20]^*1
Notes: 1. a[*]: Not an address pin but an external address
2. Can only be set in the SH7750R.
3. Can only be set in the SH7750S/SH7750R (Setting prohibited in the SH7750).
4. For details on address multiplexing, refer to appendix F, Synchronous DRAM Address
Multiplexing Tables.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 407 of 1076