HD6417750RF240DV Datasheet, PDF (503/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
Address Multiplexing: When area 2 or area 3 is designated as DRAM space, address
multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row
and column address multiplexing, to be connected to this LSI without using an external address
multiplexer circuit. Any of the five multiplexing methods shown below can be selected, by setting
bits AMXEXT and AMX2–0 in MCR for area 2 or 3 DRAM. The relationship between the
AMXEXT and AMX2–0 bits and address multiplexing is shown in table 13.15. The address
output pins subject to address multiplexing are A17 to A1. The address signals output by pins A25
to A18 are undefined.
Table 13.15 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing
AMXEXT
Setting
AMX2 AMX1
AMX0
Number
of Column
Address
Bits
Output Timing
External Address Pins
A1–A13 A14 A15 A16 A17
0
0
0
0
8 bits
Column address A1–A13 A14 A15 A16 A17
Row address A9–A21 A22 A23 A24 A25
1
9 bits
Column address A1–A13 A14 A15 A16 A17
Row address A10–A22 A23 A24 A25 A17
1
0
10 bits
Column address A1–A13 A14 A15 A16 A17
Row address A11–A23 A24 A25 A16 A17
1
11 bits
Column address A1–A13 A14 A15 A16 A17
Row address A12–A24 A25 A15 A16 A17
1
0
0
12 bits
Column address A1–A13 A14 A15 A16 A17
Row address A13–A25 A14 A15 A16 A17
Other settings
Reserved —
—
————
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 451 of 1076