HD6417750RF240DV Datasheet, PDF (590/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
CKIO
BREQ
BACK
A25–A0
CSn
RD/WR
RD
WEn
D63–D0 (write)
BS
BREQ/BSACK
BACK/BSREQ
A25–A0
CSn
RD/WR
RD
WEn
D63–D0 (write)
BS
Hi-Z
Asserted for at least 2 cycles
Hi-Z
Negated within 2 cycles
Hi-Z
Hi-Z
Hi-Z
HiZ
Hi-Z
Hi-Z
Master mode device access
Must be asserted for
at least 2 cycles
Must be negated within 2 cycles
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Slave mode device access
Master access
Slave access
Figure 13.79 Arbitration Sequence
Master access
Page 538 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013