HD6417750RF240DV Datasheet, PDF (160/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 3 Memory Management Unit (MMU)
SH7750, SH7750S, SH7750R Group
31
24 23
Address field _{1 1 1 1 0 1 1 1 0}
14 13
87
0
E
31 30 29 28
Data field
PPN
10 9 8 7 6 5 4 3 2 1 0
V PR C D
Legend:
PPN: Physical page number
V: Validity bit
E: Entry
SZ: Page size bits
D: Dirty bit
PR: Protection key data
SZ SH WT
C: Cacheability bit
SH: Share status bit
WT: Write-through bit
: Reserved bits (0 write value, undefined read value)
Figure 3.17 Memory-Mapped UTLB Data Array 1
3.7.6 UTLB Data Array 2
UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2, and the entry
is selected by bits [13:8].
In the data field, TC is indicated by bit [3], and SA by bits [2:0].
The following two kinds of operation can be used on UTLB data array 2:
1. UTLB data array 2 read
SA and TC are read into the data field from the UTLB entry corresponding to the entry set in
the address field.
2. UTLB data array 2 write
SA and TC specified in the data field are written to the UTLB entry corresponding to the entry
set in the address field.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013