HD6417750RF240DV Datasheet, PDF (119/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 2 Programming Model
A A+1 A+2 A+3
31
23
15
7
0
7
07
07
07
0
Address A _{Byte 0 Byte 1 Byte 2 Byte 3}
15
0 15
0
Address A + 4
Word 0
Word 1
31
0
Address A + 8
Longword
A + 11 A + 10 A + 9 A + 8
31
23
15
7
0
7
07
07
07
0
Byte 3 Byte 2 Byte 1 Byte 0 ^{Address A + 8}
15
0 15
0
Word 1
Word 0 Address A + 4
31
Longword
0
Address A
Big endian
Little endian
Figure 2.5 Data Formats In Memory
Note: The SH-4 does not support endian conversion for the 64-bit data format. Therefore, if
double-precision floating-point format (64-bit) access is performed in little endian mode,
the upper and lower 32 bits will be reversed.
2.6 Processor States
The SH-4 has five processor states: the reset state, exception-handling state, bus-released state,
program execution state, and power-down state.
Reset State: In this state the CPU is reset. The reset state is entered when the RESET pin goes
low. The CPU enters the power-on reset state if the MRESET pin is high, and the manual reset
state if the MRESET pin is low. For more information on resets, see section 5, Exceptions.
In the power-on reset state, the internal state of the CPU and the on-chip peripheral module
registers are initialized. In the manual reset state, the internal state of the CPU and registers of on-
chip peripheral modules other than the bus state controller (BSC) are initialized. Since the bus
state controller (BSC) is not initialized in the manual reset state, refreshing operations continue.
Refer to the register configurations in the relevant sections for further details.
Exception-Handling State: This is a transient state during which the CPU's processor state flow
is altered by a reset, general exception, or interrupt exception handling source.
In the case of a reset, the CPU branches to address H'A000 0000 and starts executing the user-
coded exception handling program.
In the case of a general exception or interrupt, the program counter (PC) contents are saved in the
saved program counter (SPC), the status register (SR) contents are saved in the saved status
register (SSR), and the R15 contents are saved in saved general register 15 (SGR). The CPU
branches to the start address of the user-coded exception service routine found from the sum of the
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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