HD6417750RF240DV Datasheet, PDF (130/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 3 Memory Management Unit (MMU)
SH7750, SH7750S, SH7750R Group
ITLB entry 0 is updated
ITLB entry 1 is updated
ITLB entry 2 is updated
ITLB entry 3 is updated
Other than the above
LRUI
[5]
[4]
[3]
[2]
[1]
[0]
1
1
1
*
*
*
0
*
*
1
1
*
*
0
*
0
*
1
*
*
0
*
0
0
Setting prohibited
Ensure that values for which “Setting prohibited” is indicated in the above table are not set at
the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0,
and therefore a prohibited setting is never made by a hardware update.
• URB: UTLB replace boundary. Bits that indicate the UTLB entry boundary at which
replacement is to be performed. Valid only when URB > 0.
• URC: UTLB replace counter. Random counter for indicating the UTLB entry for which
replacement is to be performed with an LDTLB instruction. URC is incremented each time the
UTLB is accessed. When URB > 0, URC is reset to 0 when the condition URC = URB occurs.
Also note that, if a value is written to URC by software which results in the condition URC >
URB, incrementing is first performed in excess of URB until URC = H'3F. URC is not
incremented by an LDTLB instruction.
• SQMD: Store queue mode bit. Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception in case of user access)
• SV: Single virtual mode bit. Bit that switches between single virtual memory mode and
multiple virtual memory mode.
0: Multiple virtual memory mode
1: Single virtual memory mode
When this bit is changed, ensure that 1 is also written to the TI bit.
• TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB
bits. This bit always returns 0 when read.
• AT: Address translation enable bit. Specifies MMU enabling or disabling.
0: MMU disabled
1: MMU enabled
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013