HD6417750RF240DV Datasheet, PDF (452/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles
inserted in the setup time from the address until assertion of the read/write strobe. Valid only for
SRAM interface, byte control SRAM interface, and burst ROM interface.
Bit 4n + 2: AnS0
0
1
Note: n = 6 to 0
Waits Inserted in Setup
0
1
(Initial value)
Bits 4n + 1 and 4n—Area n (6 to 0) Data Hold Time (AnH1, AnH0): When writing, these bits
specify the number of cycles to be inserted in the hold time from negation of the write strobe.
When reading, they specify the number of cycles to be inserted in the hold time from the data
sampling timing. Valid only for SRAM interface, byte control SRAM interface, and burst ROM
interface.
Bit 4n + 1: AnH1
0
1
Note: n = 6 to 0
Bit 4n: AnH0
0
1
0
1
Waits Inserted in Hold
0
1
2
3
(Initial value)
Bits 4n+3⎯Area n (4 or 1) Read-Strobe Negate Timing (AnRDH) (Setting Only Possible in
the SH7750R): When reading, these bits specify the timing for the negation of read strobe. These
bits should be cleared to 0 when a byte control SRAM setting is made. Valid only for the SRAM
interface.
Bit 4n + 3: AnRDH
0
1
Note: n = 4 or 1
Read-Strobe Negate Timing
Read strobe negated after hold wait cycles specified by WCR3.AnH bits
(Initial value)
Read strobe negated according to data sampling timing
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013