HD6417750RF240DV Datasheet, PDF (850/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 17 Smart Card Interface
SH7750, SH7750S, SH7750R Group
The receive margin in smart card mode can therefore be expressed as shown in the following
equation.
M = (0.5 – ¹ ) – (L – 0.5) F – ^{| D – 0.5 |} (1 + F) × 100%
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L =10)
F: Absolute deviation of clock frequency
From the above equation, if F = 0 and D = 0.5, the receive margin is 49.866%, as given by the
following equation.
When D = 0.5 and F = 0:
M = (0.5 – 1/2 × 372) × 100% = 49.866%
(2) Retransfer Operations
Retransfer operations are performed by the SCI in receive mode and transmit mode as described
below.
Retransfer Operation when SCI is in Receive Mode: Figure 17.11 illustrates the retransfer
operation when the SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is
automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt
request is generated. The PER bit in SCSSR1 should be cleared to 0 before the next parity bit
is sampled.
2. The RDRF bit in SCSSR1 is not set for a frame in which an error has occurred.
3. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is not set to
1.
4. If no error is found when the received parity bit is checked, the receive operation is judged to
have been completed normally, and the RDRF bit in SCSSR1 is automatically set to 1. If the
RIE bit in SCSCR1 is enabled at this time, an RXI interrupt request is generated.
5. When a normal frame is received, the pin retains the high-impedance state at the timing for
error signal transmission.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013