HD6417750RF240DV Datasheet, PDF (766/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 15 Serial Communication Interface (SCI)
SH7750, SH7750S, SH7750R Group
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCSSR1 to 0
End
Figure 15.21 Sample Serial Reception Flowchart (2)
In serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with serial clock input or output.
2. The received data is stored in SCRSR1 in LSB-to-MSB order.
After reception, the SCI checks whether the RDRF flag is 0, indicating that the receive data
can be transferred from SCRSR1 to SCRDR1.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If
a receive error is detected in the error check, the operation is as shown in table 15.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
Also, as the RDRF flag is not set to 1 when receiving, the flag must be cleared to 0.
3. If the RIE bit in SCRSR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full
interrupt (RXI) request is generated. If the RIE bit in SCRSR1 is set to 1 when the ORER flag
changes to 1, a receive-error interrupt (ERI) request is generated.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013