HD6417750RF240DV Datasheet, PDF (335/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 9 Power-Down Modes
9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only)
Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode.
The CA pin level must be kept low while in hardware standby mode.
After setting the RESET pin level low, the clock starts when the CA pin level is switched to high.
CKIO
CA
RESET
SCK2
(High)
STATUS
Normal^*1
Standby^*3
*2
Reset
0–10 Bcyc
Waiting for end of bus cycle
0–10 Bcyc
Notes: 1. Same at sleep and reset.
2. Undefined
3. High impedance when STBCR2. STHZ = 0
Figure 9.12 Hardware Standby Mode Timing
(When CA = Low in Normal Operation)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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