HD6417750RF240DV Datasheet, PDF (824/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
SH7750, SH7750S, SH7750R Group
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
Base clock
–7.5 clocks
+7.5 clocks
Receive data
(RxD2)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = (0.5 – ¹ ) – (L – 0.5) F – ^{| D – 0.5 |} (1 + F) × 100% ^{...................... (1)}
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
M = (0.5 – 1 / (2 × 16)) × 100% = 46.875% ................................................ (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013