HD6417750RF240DV Datasheet, PDF (798/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
SH7750, SH7750S, SH7750R Group
SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR2 can be read or written to by the CPU at all times.
SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 11—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 10 to 8 (SH7750)—Reserved: These bits are always read as 0, and should only be written
with 0.
Bits 10 to 8 (SH7750S, SH7750R)—RTS2 Output Active Trigger (RSTRG2, RSTG1, and
RSTG0): These bits output the high level to the RTS2 signal when the number of received data
stored in the receive FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the
table below.
Bit 10: RSTRG2 Bit 9: RSTRG1
0
0
1
1
0
1
Bit 8: RSTRG0
0
1
0
1
0
1
0
1
RTS2 Output Active Trigger
15
(Initial value)
1
4
6
8
10
12
14
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013