HD6417750RF240DV Datasheet, PDF (258/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 6 Floating-Point Unit (FPU)
SH7750, SH7750S, SH7750R Group
Modifying Software
Problem types (1), (2), and (3): Deal with problem types (1), (2), and (3) in table 6.3 using
software based on the flowchart below.
Adjust the source operands by multiplying them by 2 , ¹⁵³⁶ then calculate them as normalized
numbers.
In the case of problem type (1), if the Divide by Zero exception is enabled, the divide by zero
exception trap is generated and the destination register does not change. If the Divide by Zero
exception is disabled, the contents of the destination register become infinity with the sign based
on the input operands.
START
Save source DRn
FDIV DRm, DRn
Is operation result
Yes
±INF or ±0?
No
Problem type (1), (2), ^Yes
or (3)?
No
Restore source DRn
DRm × 2¹⁵³⁶, DRn × 2¹⁵³⁶
FDIV DRm, DRn
END
Problem type (7): In the case of problem type (7) in table 6.3, no FPU error occurs. The operation
result is correct and there is no need for a software workaround.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013