HD6417750RF240DV Datasheet, PDF (199/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 4 Caches
Example 2: When an instruction that generates an exception branches using a branch instruction
Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.
Instruction 2 ; May be executed if instruction 1 is a delay slot instruction and an instruction to store data to SQ.
Instruction 3
Instruction 4
Instruction 5
Instruction 6
Instruction 7 (branch destination of instruction 1)
; May be executed if an SQ access instruction.
Instruction 8 ; May be executed if an SQ store instruction.
Example 3: When an instruction that generates an exception does not branch using a branch instruction
Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.
Instruction 2 ; May be executed if an SQ store instruction.
Instruction 3 ; May be executed if an SQ store instruction.
Instruction 4 ; May be executed if an SQ store instruction.
Instruction 5
To recover from this problem it is necessary that conditions A and B be satisfied.
A: After the PREF instruction to transfer data from the store queue (SQ0, SQ1) to external
memory, a store instruction for the same store queue must be executed, and conditions (1) and
(2) below must be satisfied.
(1) Three NOP instructions^*1 must be inserted between the above two instructions.
(2) There must not be a PREF instruction to transfer data from the store queue to external
memory in the delay slot of the branch instruction.
B: There must be no PREF instruction to transfer data from the store queue to external memory
executed in the exception handling routine.
If such an instruction is executed, and if there is a store to the store queue instruction among
the four instructions^*2 at the address referred to by SPC, the data transferred to external
memory by the PREF instruction may indicate that execution of the store instruction has
completed.
Notes: 1. If there are other instructions between the above two instructions, the problem can be
avoided if the other instructions and NOP instructions together total three or more
instructions.
2. If the instruction at the address referred to by SPC is a branch instruction the two
instructions at the branch destination may be affected.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 147 of 1076