HD6417750RF240DV Datasheet, PDF (682/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 14 Direct Memory Access Controller (DMAC)
SH7750, SH7750S, SH7750R Group
Four requests can be queued
CLK
1st 2nd 3rd 4th
DBREQ
BAVL
TR
Handshaking is necessary
to send additional requests
5th
A25–A0
D63–D0
RAS,
CAS, WE
TDACK
ID1, ID0
CA
CA
CA
CA
D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2
RD
RD
RD
RD
Must be ignored
(no request transmitted)
Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2
Page 630 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013