HD6417750RF240DV Datasheet, PDF (144/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 3 Memory Management Unit (MMU)
SH7750, SH7750S, SH7750R Group
Instruction access to virtual address (VA)
VA is
VA is
in P4 area in P2 area
VA is
in P1 area
VA is in P0, U0,
or P3 area
Access prohibited
0
CCR.ICE?
1
No
MMUCR.AT = 1
Yes
No
VPNs match
and V = 1
Yes
Search UTLB
Hardware ITLB
miss handling
Match?
No
Yes _{Record in ITLB}
Instruction TLB
miss exception
0
No
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
Yes
No
VPNs match
and ASIDs match and
V=1
Yes
Only one
No
entry matches
Yes
0 (User)
PR?
1
SR.MD?
1 (Privileged)
Instruction TLB
multiple hit exception
Instruction TLB protection
violation exception
C=1
No
and CCR.ICE = 1
Yes
Cache access
Memory access
(Non-cacheable)
Figure 3.11 Flowchart of Memory Access Using ITLB
Page 92 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013