HD6417750RF240DV Datasheet, PDF (455/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
Bits 26 to 24, 22, and 18—Reserved: These bits are always read as 0, and should only be written
with 0.
Bit 23—CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set.
Bit 23: TCAS
0
1
CAS Negation Period
1
2
(Initial value)
Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the DRAM interface is selected,
these bits specify the minimum number of cycles until RAS is asserted again after being negated.
When the synchronous DRAM interface is selected, these bits specify the minimum number of
cycles until the next bank active command after precharging.
Note: For setting values and the period during which no command is issued, see 22.3.3, Bus
Timing.
Bit 21: TPC2
Bit 20: TPC1
Bit 19: TPC0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note: * Inhibited in RAS down mode.
RAS Precharge Interval
DRAM
Synchronous DRAM
0
1* (Initial value)
1
2
2
3
3
4*
4
5*
5
6*
6
7*
7
8*
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 403 of 1076