HD6417750RF240DV Datasheet, PDF (559/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
Card 1
on CS5
Virtual
address space
Common
memory 1
Common
memory 2
Attribute memory
I/O space 1
I/O space 2
Common memory
(64 MB)
Access
by CS5 wait
controller
Access
by CS6 wait
controller
Virtual
address space
1 KB IO 1
page
Physical I/O
addresses
IO 1
IO 2
Attribute memory
(64 MB)
.
.
.
I/O space
(64 MB)
IO 2
1 KB
page
Different virtual pages
mapped to the same
physical page
Example of I/O spaces with different cycle times
(less than 1 KB)
Card 2
on CS6
.
.
.
The page size can be 1 KB, 4 KB, 64 KB, or 1 MB.
Example of PCMCIA interface mapping
Figure 13.53 PCMCIA Space Allocation
I/O Card Interface Timing: Figures 13.54 and 13.55 show the timing for the PCMCIA I/O card
interface.
When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic
sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set, if the
IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits
in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being
executed, followed automatically by a data access for the remaining 8 bits. Dynamic bus sizing is
also performed in the case of byte-size access to address 2n + 1.
Figure 13.56 shows the basic timing for dynamic bus sizing.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 507 of 1076